1. Field of the Invention
The present invention relates to the fabrication of high-quality tunnel oxide layers, and more particularly, to the fabrication of tunnel capacitors.
1. Description of the Related Art
Conventional oxide layers, particularly tunnel oxides for tunnelling EEPROMs, have poor endurance after the oxide layers are heated to temperatures of 1100.degree. C. or more during fabrication steps following the formation of the oxide layer. In particular, in the fabrication of EEPROMs, a tunnel oxide is provided on a substrate and a polysilicon floating gate is deposited on the tunnel oxide and then doped and patterned. Then, an inter-gate oxide is thermally grown at the exposed surface of the control gate at a temperature of 1100.degree. C. or greater. A control gate is provided on the inter-gate oxide.
Several problems may occur with the tunnel oxide in such an EEPROM. First, if the tunnel oxide is grown in a gaseous environment including HC1, the surface of the substrate is roughened due to etching by the HC1. The roughening of the surface of the substrate creates physical discontinuities which cause charge concentrations in the regions of the discontinuities. Charge concentrations if large enough can exceed the breakdown voltage of the tunnel oxide.
Second, conventional tunnel oxides have physical defects, e.g., cracks, which allow the dopant ions in the control gate to migrate across the tunnel oxide to the substrate during the high temperature cycle utilized to grow the inter-gate oxide, thereby ruining the device.
Conventional tunnel oxide layers suffer from a reduction in the breakdown field (breakdown voltage normalized for thickness), low fluence (capacitance normalized for the area of the capacitor), and the inability to be stressed to high breakdown fields without catastrophic failure. These problems also occur with gate oxide layers in EPROMs and other MOS devices.